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SM5819AF seiko npc corporation ? 6-channel dsd-pcm converter overview the SM5819AF is a 6-channel dsd data (64fs) to 4fs, 2fs or fs pcm data converter. during conversion, deci- mation ?tering is performed using a ?ter with selectable ?ed coef?ients (3 sets). also, dsd inputs and pcm outputs are available for use in master/slave clock mode operation, in a wide range of system con?ura- tions, making it easy to construct a multi-channel dsd/pcm reproduction system. features 512fs (22.5792mhz, fs = 44.1khz), 1:2 to 2:1 duty master clock dsd input and pcm output clock master/slave switching 3-system external data input (3-wire format), pcm output data/bck/lrck external input and internal ?ter output switching (bck and lrck are common to all 3 external pcm data inputs) decimation ?ter coef?ients fixed coef?ients: 4fs-1/2fs-1/fs-1 pcm output mute operation pcm output format: [msb-?st left-justi?d 32- bit] or [iis 32-bit] (iis 32-bit output bit clock frequency = 64 word clock frequency) fir ?ter coef?ients 64fs 4fs/2fs/fs: 480th-order (6-channel) rom coef?ients: 24 valid data bits (4-bit msb extension at 4fs, 5-bit msb extension at 2fs/fs) + 6db dsd gain switching function external/internal system clock output switching 3.3v (3.0 to 3.6v) and 2.5v (2.3 to 2.7v) power supplies ? 40 to 85 c operating temperature range 48-pin qfp package applications multi-channel sa-cd players sa-cd-compatible av ampli?rs ordering information pinout (top view) package dimensions (unit: mm) device package SM5819AF 48 -pin qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vddl sel1fs sel4fs dsgain xmtpcm vddh test1 selext vss test2 test3 tout1 vddl dirpck fmtpcm vss mckout vddh pbck plrck poslr pocsw poflr vss vddl mck tout2 vss eximck vddh exibck exilrck exislr exicsw exiflr vss vddl dsbck dsifl dsifr dsict dsisw dsisl dsisr dirdsck sync init vss 9 0.4 7 0.1 9 0.4 7 0.1 0.5 0.2 0.125 ? 0.025 + 0.075 1.4 0.1 1.7 max 0.1 0.5 0 ~ 10 0.18 ? 0.05 + 0.09 0.08
SM5819AF seiko npc corporation ? pin description no. name i/o property 1 input voltage description 1 vddl ?? 2.5v core power supply 2 sel1fs i pd 3.3v pcm output rate select 1 l: 2fs/4fs, h: fs 3 sel4fs i pd 3.3v pcm output rate select 2 l: 2fs, h: 4fs 4 selext i pd 3.3v fs/2fs/4fs output and external data output select l: fs/2fs/4fs data, h: external data (exi**) 5 dsgain i pd 3.3v dsd signal gain setting l: 100% modulation = 0db, h: 50% modulation = 0db 6 xmtpcm i pd 3.3v pcm output mute control input l: mute on, h: mute off 7 vddh ?? 3.3v i/o power supply 8 test1 i pd 3.3v test input 1 (must be open or tie low for normal operation) 9 test2 i pd 3.3v test input 2 (must be open or tie low for normal operation) 10 test3 i pd 3.3v test input 3 (must be open or tie low for normal operation) 11 tout1 o ?? test output 1 12 vss ?? ? ground 13 vddl ?? 2.5v core power supply 14 dirpck i pd 3.3v pcm output pbck/plrck i/o select l: output (master mode), h: input (slave mode) 15 fmtpcm i pd 3.3v pcm output format select l: msb-?st left-justi?d 32-bit, h: iis 32-bit 16 vss ?? ? ground 17 mckout o 12ma ? system clock output (selected by selext) 18 vddh ?? 3.3v i/o power supply 19 pbck i/o s, 6ma 3.3v pcm output bck bit clock 20 plrck i/o s, 6ma 3.3v pcm output lrck word clock 21 poslr o 2ma ? pcm data output: surround left/right-channel 22 pocsw o 2ma ? pcm data output: center/subwoofer channel 23 poflr o 2ma ? pcm data output: front left/right-channel 24 vss ?? ? ground 25 vddl ?? 2.5v core power supply 26 tout2 o ?? test output 2 27 mck i ? 3.3v master clock input: 512fs (22.5792mhz, fs = 44.1khz) 28 vss ?? ? ground 29 eximck i ? 3.3v external system clock input 30 vddh ?? 3.3v i/o power supply 31 exibck i s 3.3v external pcm data bck bit clock input 32 exilrck i s 3.3v external pcm data lrck word clock input 33 exislr i ? 3.3v external pcm data input: surround left/right-channel 34 exicsw i ? 3.3v external pcm data input: center/subwoofer channel 35 exiflr i ? 3.3v external pcm data input: front left/right-channel 36 vss ?? ? ground 37 vddl ?? 2.5v core power supply 38 dsbck i/o s, 6ma 3.3v dsd data input bit clock. controlled by dirdsck
SM5819AF seiko npc corporation ? 39 dsifl i ? 3.3v dsd data input: front left-channel 40 dsifr i ? 3.3v dsd data input: front right-channel 41 dsict i ? 3.3v dsd data input: center channel 42 dsisw i ? 3.3v dsd data input: subwoofer channel 43 dsisl i ? 3.3v dsd data input: surround left-channel 44 dsisr i ? 3.3v dsd data input: surround right-channel 45 dirdsck i pd 3.3v dsbck i/o select l: input (slave), h: output (master) 46 sync i s, pu 3.3v forced synchronization input (active-high edge) 47 init i s, pu 3.3v initialization input: active-low, resync on ? ? 48 vss ?? ? ground 1. s = schmitt, pu = pull-up resistor, pd = pull-down resistor, ma = output current no. name i/o property 1 input voltage description
SM5819AF seiko npc corporation ? block diagram dsifl dsifr dsict dsisl dsisr dsisw dsgain sel1fs sel4fs xmtpcm exiflr exislr fir filter and down sampling unit pcm mute rom 24bit 720word (fs 240w) (2fs 240w) (4fs 240w) exicsw int/ext. data select fmtpcm poflr poslr pocsw int/ext. clock select clock generator and timing control selext pbck plrck mckout sync init dirdsck dsbck mck (internal clocks) dirpck test1 test2 test3 tout2 test control tout1 exilrck exibck eximck pcm i/f
SM5819AF seiko npc corporation ? specifications absolute maximum ratings v ss = 0v recommended operating conditions v ss = 0v dc electrical characteristics v ddh = 3.0 to 3.6v, v ddl = 2.3 to 2.7v, v ss = 0v, t opr = ?40 to 85 c unless otherwise noted. pin summary parameter symbol rating unit supply voltage 1 v ddh ?0.3 to 4.0 v supply voltage 2 v ddl ?0.3 to 3.0 v input voltage (3.3v) v in ?0.3 to v ddh + 0.5 v power dissipation p d 200 mw storage temperature range t stg ?55 to 125 c parameter symbol rating unit supply voltage 1 v ddh 3.0 to 3.6 v supply voltage 2 v ddl 2.3 to 2.7 v operating temperature t opr ?40 to 85 c parameter pin symbol condition rating unit min typ max current consumption 1 vddh i ddh all pins no load 5ma current consumption 2 vddl i ddl 30ma input voltage ?" level (*1) v ih v ddh = 3.6v 2.0 v ?" level (*1) v il v ddh = 3.0v 0.8 v schmitt-trigger voltage positive (*2) v t+ 1.1 2.4 v negative (*2) v t 0.6 1.8 v hysteresis voltage (*2) v h 0.1 v output voltage "h" level (*3) v oh i oh = ?2ma (type1) i oh = ?6ma (type2) i oh = ?12ma (type3) v ddh ?0.4 v "l" level (*3) v ol i ol = 2ma (type1) i ol = 6ma (type2) i ol = 12ma (type3) 0.4 v input leakage current (*1, 2) i li ?5 5 a pull-down resistor (*4) r pd v i = v ddh 60 120 288 k ? pull-up resistor (*5) r pu v i = v ss 60 120 288 k ? (*1) input pins and bidirectional (input/output) pins in input mode (*2) inputs with schmitt characteristic and bidirectional (input/output) pins in input mode (*3) output pins and bidirectional (input/output) pins in output mode type 3: mckout type 2: dsbck, pbck, plrck type 1: outputs excluding those above (*4) inputs with pull-down resistor (*5) inputs with pull-up resistor
SM5819AF seiko npc corporation ? ac electrical characteristics v ddh = 3.0 to 3.6v, v ddl = 2.3 to 2.7v, v ss = 0v, t opr = ?40 to 85 c, fs = 44.1khz unless otherwise noted. when dsbck and plrck clocks are supplied by external clock input, their frequencies are related to the mck input frequency by the following frequency divider ratios. (dsbck) cycle = 8 mck cycle (64fs) (plrck) cycle [4fs mode] = 128 mck cycle (4fs) (plrck) cycle [2fs mode] = 256 mck cycle (2fs) (plrck) cycle [fs mode] = 512 mck cycle (fs) system clock mck pin external system clock eximck pin parameter symbol rating unit min typ max "h"-level pulsewidth t mcwh 13 ns "l"-level pulsewidth t mcwl 13 ns pulse cycle t mcy 40 44.29 (1/512fs) ns rise/fall time t r , t f 10 ns parameter symbol rating unit min typ max "h"-level pulsewidth t ecwh 13 ns "l"-level pulsewidth t ecwl 13 ns pulse cycle t ecy 40 ns rise/fall time t er , t ef 10 ns 0.9v ddh mck t r t f t mcwh t mcwl t mcy 0.5v ddh 0.1v ddh 0.9v ddh eximck t er t ef t ecwh t ecwl t ecy 0.5v ddh 0.1v ddh
SM5819AF seiko npc corporation ? dsd input dsbck pin dsifl, dsifr, dsisl, dsisr, dsict, dsisw pins note. dsd clock pulsewidth and dsd clock pulse cycle when dsbck is in input mode. note. the data, with dsbck timing above, enters the internal circuits on the falling edge of the mck clock. consequently, if the timing changes, the circuit must be resynchronized using init or sync. parameter symbol rating unit min typ max dsd clock pulsewidth t dscw 150 177.16 ns dsd clock pulse cycle t dscy 300 354.31 (1/64fs) ns dsd data setup time t dss 50 ns dsd data hold time t dsh 50 ns dsi**: dsifl, dsifr, dsisl, dsisr, dsict, dsisw pins dsbck t dscw t dscw t dscy t dss t dsh dsi**
SM5819AF seiko npc corporation ? pcm output plrck, pbck, poflr, poslr, pocsw pins note. the pcm output relationship applies when the external inputs (exi**) are not in through mode. note. fs/2fs/4fs bit clock and word clock relationship applies when pbck and plrck are in input mode. parameter symbol rating unit min typ max bck clock pulsewidth 4fs t pbcw 40 44.29 ns 2fs 40 88.58 ns fs 40 177.15 ns bck clock pulse cycle 4fs t pbcy 80 88.58 (1/256fs) ns 2fs 80 177.15 (1/128fs) ns fs 80 354.31 (1/64fs) ns word ck setup time t plbs 30 ns word ck hold time t plbh 10 ns bit ck data delay time t pbdly 0 15 ns word ck data delay time t pldly 0 15 ns po**: poflr, poslr, pocsw pins t pbcw pbck t pbcw t pbcy plrck t plbh t plbs t pldly t pbdly po**
SM5819AF seiko npc corporation ? clock outputs mckout, dsbck, plrck, pbck pins note. applies when mck clock is output on mckout in through mode. note. applies when each word/bit clock on dsbck, pbck, plrck is in output mode. through-mode output mckout, pbck, plrck, poflr, poslr, pocsw pins parameter symbol rating unit min typ max mckout output delay time t ckodly 0 10 ns word/bit clock output delay time t ckdly 0 10 ns through inputs through outputs condition t thdly max unit eximck mckout pcm outputs with external inputs selected 10 ns exibck pbck 10 ns exiwck plrck 10 ns exiflr poflr 15 ns exislr poslr 15 ns exicsw pocsw 15 ns mckout t ckodly t ckdly word/bit clock outputs mck t ckodly through mode output t thdly through mode input t thdly
SM5819AF seiko npc corporation ?0 initialization and resynchronization init, sync pins parameter symbol rating unit min typ max initialization time t intm 6 t mcy ns resynchronization pulsewidth t sycw 6 t mcy ns t intm init sync t sycw t intm vddh 3.0v
SM5819AF seiko npc corporation ?1 functional description data input/output formats dsd input format dsd input data is read in on the rising edge of the dsbck bit clock. pcm output format the pcm output format can be assigned to either of two types below using fmtpcm. the output data is in 32- bit 2s complement form. the plrck and pbck frequencies are set in response to the fs/2fs/4fs switch mode. however, when external inputs are selected, the inputs are passed to the output in through mode, regardless of the assigned format. (1) msb-?st left-justi?d 32-bit (fmtpcm = ?? if more than 32 bit clock cycles are input during a word clock cycle high-level or low-level pulse, all bits after the 32nd bit are output as ?? when plrck and pbck are set to output mode, the number of bit clock cycles during a word clock high- level or low-level pulse is ?ed at 32. (2) iis 32-bit (fmtpcm = ?? in this format, there are 32 bit clock cycles per word clock cycle regardless of the input/output settings. dsi**: dsifl, dsifr, dsisl, dsisr, dsict, dsisw pins po**: poflr, poslr, pocsw pins po**: poflr, poslr, pocsw pins dsbck dsi** (1/64fs) plrck (1/fs, 1/2fs, or 1/4fs) 31 30 29 28 msb pbck po** 2 1 0 31 30 lsb 29 28 2 1 0 31 30 lch (poslr, poflr) center (pocsw) rch (poslr, poflr) subwoofer (pocsw) plrck (1/fs, 1/2fs, or 1/4fs) 0 31 30 29 4 3 2 0 31 30 msb 0 31 lsb pbck po** 29 4 3 2 rch (poslr, poflr) subwoofer (pocsw) lch (poslr, poflr) center (pocsw) 1 1 1
SM5819AF seiko npc corporation ?2 data output selection pcm output selection the pcm output and decimation ?ter processing is set by sel4fs, sel1fs and selext, as shown in the following table. the external data setting (selext) has priority over the 4fs/2fs/fs selection setting (sel1fs, sel4fs). also, the fs setting (sel1fs) has priority over the 4fs/2fs setting (sel4fs). clock input/output selection and resynchronization operation dsd clock input/output switching the dsd input bit clock (dsbck) can be switched between input and output by dirdsck. pcm clock input/output switching the pcm output word clock (plrck) and bit clock (pbck) can be switched between input and output by dirpck. ho we v er , when e xternal data is selected using selext , the clocks plrck and pbck are switched to outputs, re g ardless of the dirpck setting, thus care must be e x ercised with e xternal connections. setting pcm output system clock output filter processing sel1fs sel4fs selext poflr poslr pocsw plrck pbck mckout lhl dsifl dsifr dsisl dsisr dsict dsisw 4fs mck 4fs 480th-order lll dsifl dsifr dsisl dsisr dsict dsisw 2fs mck 2fs 480th-order h l or h l dsifl dsifr dsisl dsisr dsict dsisw fs mck fs 480th-order l or h l or h h exiflr exislr exicsw exilrck exibck eximck invalid setting i/o state dirdsck dsbck l input (slave) h output (master) setting i/o state dirpck plrck pbck l output (master) h input (slave)
SM5819AF seiko npc corporation ?3 input clock sync operation and resynchronization the internal computation and interface processing for data output is event driven, with the word boundary edge of the word clock as the trigger. this ensures the output signals are synchronized, regardless of the word clock and bit clock input/output settings. the dsd input comprises data read into a buffer on the rising edge of the dsbck bit clock (buf_a) and data in another buffer internally delayed by half a bit clock cycle (buf_b), and then a buffer is selected when the pcm output event occurs in order to avoid dsd input signal transitions. synchronization of whichever data buffer is selected occurs when the word boundary edge of the word clock is detected after the ?st dsbck falling edge following a rising edge on init or sync. 1) on the ?st dsbck falling edge after a rising edge of sync or init, (in_phase) is a phase reference sig- nal for input data buffer selection. 2) then, the input data buffer selected is determined by the logic level of in_phase when the ?st plrck word boundary edge is detected. when synchronization is adjusted using init or sync (resynchronization), 1 dsd data unit may be lost or repeated depending on the phase difference between input/output clocks. the individual outputs should be muted by a minimum interval, given below, to avoid these data glitches. [4fs pcm output] 36 clock cycles in plrck (4fs) mode [2fs pcm output] 18 clock cycles in plrck (2fs) mode [fs pcm output] 10 clock cycles in plrck (fs) mode dsi**: dsifl, dsifr, dsisl, dsisr, dsict, dsisw pins figure 1. input timing synchronization operation using init and sync snyc/init dsi** d (n) d (n+1) d (n+2) d (n+3) d (n+3) dsbck (buf_a) da (n) da (n+1) da (n+2) da (n+3) (buf_b) db (n) db (n+1) db (n+2) db (n+2) (in_phase) (pcm_sel) plrck (word boundary edge) (filter input) db (n+1) db (n+2) db (n-1) (select "buf_a") da (n-1) da (n) da (n+1)
SM5819AF seiko npc corporation ?4 external input data and external system clock output switching (1) switching to external input data when selext is switched low to high, the pcm data output is immediately switched to external input data. plrck and pbck are similarly switched immediately to exilrck and exibck in through mode, respectively, regardless of the dirpck setting. (2) switching to external system clock the mckout system clock output can be switched between mck and eximck using selext, as given below. selext = ?? mck output selext = ?? eximck output note that neither mck nor eximck clock should be stopped during the switching interval to prevent a micro-pulse being generated when switching. the switching interval lasts from when selext changes state until both clocks have made 4 transitions. during this interval, the low-level clock pulsewidth of the ?st clock is extended until the rising edge of the second clock occurs. when the switching interval ends, the unused clock may then be stopped. figure 2. mck eximck switching figure 3. eximck mck switching mck eximck selext mckout off on (switching time) (mck off) (eximck on) mck eximck selext mckout off on (switching time) (mck on) (eximck off)
SM5819AF seiko npc corporation ?5 dsd gain switching the pcm output can be adjusted such that 0db corresponds to 50% modulation level dsd input signal using dsgain, as given below. dsgain = ? : 100% modulation = 0db (pcm) dsgain = ? : 50% modulation = 0db (pcm) * with + 6db internal ampli?ation note. when dsgain = ?? note that any input dsd signal with modulation of 50% level or higher will be amplitude limited, resul ting in output signal clip- ping. mute function the pcm outputs can be muted using xmtpcm, as given below. muting is applied immediately before output. when pcm muting is set on, the pcm outputs are directly set to value ?? xmtpcm = ? : all pcm outputs muting on xmtpcm = ? : all pcm outputs muting off the mute function is only active for internal computation of fs/2fs/4fs output. it is inactive for external input to output connection in through mode. initialization operation the power must be applied in order of vddl and vddh. please avoid the continuous power supply injection of only vddh. (less than 1 second) after power is applied, init must be held low for the rated interval to initialize the device. during initializa- tion, the outputs have the following states. when init goes high, synchronization operation begins as described in the section ?nput clock sync opera- tion and resynchronization? note that if the pcm signal muting is on during initialization, muting operation continues until it is released. the system clock input on mck must be applied during initialization. figure 4. dsd modulation level pin state pcm data outputs low in internal data output mode external input to output connection in through mode dsbck high in output (master) mode pbck high in internal data output mode external bit clock input to output connection in through mode plrck low in 32-bit left-justi?d output mode high in iis output mode external word clock input to output connection in through mode mckout mck or eximck, whichever is currently selected. +1.0 +0.5 0 -0.5 -1.0 [00000000h] [7fffffffh] [7fffffffh] [80000000h] [80000000h] [00000000h] 0db when dsgain="h" 0db when dsgain="l"
SM5819AF seiko npc corporation ?6 built-in filter characteristics filter mode cutoff characteristics ? 180 ? 170 ? 160 ? 150 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 0 10 20 30 40 50 60 70 80 90 100 [khz] [db] fs 2fs 4fs fs 2fs 4fs 0 10 20 30 40 50 60 70 [khz] [db] ? 5 ? 4 ? 3 ? 2 ? 1 0
SM5819AF seiko npc corporation ?7 filter mode ripple characteristics fs 2fs 4fs ? 0.005 ? 0.010 ? 0.015 ? 0.020 ? 0.025 ? 0.030 0.000 0 5 10 15 20 25 30 35 40 45 50 [db] [khz]
SM5819AF seiko npc corporation ?8 nc0210ce 2006.04 please pay your attention to the following points at time of using the products shown in this document. the products shown in this document (hereinafter ?roducts? are not intended to be used for the apparatus that exerts harmful in?ence on human lives due to the defects, failure or malfunction of the products. customers are requested to obtain prior written agreeme nt for such use from seiko npc corporation (hereinafter ?pc?. customers shall be solely responsible for, and indemnify and hold npc free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. npc reserves the right to change the speci?ations of the products in order to improve the characteristic or reliability thereof. npc makes no claim o r warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. therefore, npc shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in t his document. any descriptions including applications, circuits, and the parameters of the products in this document are for reference to use the products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modi?ation. customers are requested not to export or re-export, directly or indirectly, the products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. seiko npc corporation 15-6, nihombashi-kabutocho, chuo-ku, tokyo 103-0026, japan telephone: +81-3-6667-6601 facsimile: +81-3-6667-6611 http://www.npc.co.jp/ email: sales @ npc.co.jp

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